Difference between revisions of "Nxp chip library routines"

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     449        pGPIO->NOT[port] = (1 << pin);^M
 
     449        pGPIO->NOT[port] = (1 << pin);^M
 
     450 }^M
 
     450 }^M
 +
</pre>
  
 +
So where is <code>pGPIO</code> defined?
 +
 +
 +
<!-- comment -->
 +
 +
=== [[#top|^]] LPC_GPIO_TYPEDEF ===
 +
 +
<pre>
 +
$ pwd
 +
 +
.../Firmware/V1_1$
 +
 +
$ grep -nr LPC_GPIO_TypeDef ./* | grep LPC11
 +
 +
./LPC11xx.h:295:} LPC_GPIO_TypeDef;
 +
./LPC11xx.h:490:#define LPC_GPIO0            ((LPC_GPIO_TypeDef  *) LPC_GPIO0_BASE )
 +
./LPC11xx.h:491:#define LPC_GPIO1            ((LPC_GPIO_TypeDef  *) LPC_GPIO1_BASE )
 +
./LPC11xx.h:492:#define LPC_GPIO2            ((LPC_GPIO_TypeDef  *) LPC_GPIO2_BASE )
 +
./LPC11xx.h:493:#define LPC_GPIO3            ((LPC_GPIO_TypeDef  *) LPC_GPIO3_BASE )
 +
Binary file ./Release/Obj/sysconfig_LPC11xx.pbi matches
 +
./initial-firmware-works/Unit_Test/apptask/LPC11xx.h:192:} LPC_GPIO_TypeDef;
 +
./initial-firmware-works/Unit_Test/apptask/LPC11xx.h:204:extern LPC_GPIO_TypeDef gpio;
 +
./initial-firmware-works/Unit_Test/px3_system/LPC11xx.h:192:} LPC_GPIO_TypeDef;
 +
./initial-firmware-works/Unit_Test/px3_system/LPC11xx.h:204:extern LPC_GPIO_TypeDef gpio;
 +
./initial-firmware-works/FloatingPoint/LPC11xx.h:295:} LPC_GPIO_TypeDef;
 +
./initial-firmware-works/FloatingPoint/LPC11xx.h:490:#define LPC_GPIO0            ((LPC_GPIO_TypeDef  *) LPC_GPIO0_BASE )
 +
./initial-firmware-works/FloatingPoint/LPC11xx.h:491:#define LPC_GPIO1            ((LPC_GPIO_TypeDef  *) LPC_GPIO1_BASE )
 +
./initial-firmware-works/FloatingPoint/LPC11xx.h:492:#define LPC_GPIO2            ((LPC_GPIO_TypeDef  *) LPC_GPIO2_BASE )
 +
./initial-firmware-works/FloatingPoint/LPC11xx.h:493:#define LPC_GPIO3            ((LPC_GPIO_TypeDef  *) LPC_GPIO3_BASE )
 +
./initial-firmware-works/Obsolete (FixedPoint)/LPC11xx.h:295:} LPC_GPIO_TypeDef;
 +
./initial-firmware-works/Obsolete (FixedPoint)/LPC11xx.h:490:#define LPC_GPIO0            ((LPC_GPIO_TypeDef  *) LPC_GPIO0_BASE )
 +
./initial-firmware-works/Obsolete (FixedPoint)/LPC11xx.h:491:#define LPC_GPIO1            ((LPC_GPIO_TypeDef  *) LPC_GPIO1_BASE )
 +
./initial-firmware-works/Obsolete (FixedPoint)/LPC11xx.h:492:#define LPC_GPIO2            ((LPC_GPIO_TypeDef  *) LPC_GPIO2_BASE )
 +
./initial-firmware-works/Obsolete (FixedPoint)/LPC11xx.h:493:#define LPC_GPIO3            ((LPC_GPIO_TypeDef  *) LPC_GPIO3_BASE )
 +
</pre>
 +
 +
 +
<!-- comment -->
 +
 +
== Using Timers As Pulsewidth Modulators ==
 +
 +
Findings to go here later . . .
 +
 +
<!--
 +
<pre>
 +
./io_tmr16b1.c:89:// Enable/disable interrupts for PWM:
 +
./io_tmr16b1.h:9:    Using this driver for PWM:
 +
./io_tmr16b1.h:13:    3) Reset the PWM system by calling IO_TMR16B1_ResetPWM(),
 +
./io_tmr16b1.h:14:    4) Enable PWM channels by calling IO_TMR16B1_EnablePWM(),
 +
./io_tmr16b1.h:15:    5) Start PWM by calling IO_TMR16B1_StartPWM() and supplying
 +
./io_tmr16b1.h:17:    6) Set and change the PWM level by calling IO_TMR16B1_SetPwmLevel().
 +
./io_tmr16b1.h:19:    When a match register matches (during PWM, for example), a
 +
./io_tmr16b1.h:43:void IO_TMR16B1_EnablePWM(tmr16b1_chan_t chan);
 +
./io_tmr16b1.h:44:void IO_TMR16B1_ResetPWM(void);
 +
./io_tmr16b1.h:45:void IO_TMR16B1_StartPWM(uint16_t resolution);
 +
./io_tmr32b0.c:46:    // Configure PWM output on channels 0, 1, or 2.
 +
./io_tmr32b0.c:49:void IO_TMR32B0_EnablePWM(tmr32b0_chan_t chan)
 +
./io_tmr32b0.c:53:        case TMR32B0_CHAN_0: LPC_TMR32B0->PWMC |= TMR_PWM_ENA_MR0; break;
 +
./io_tmr32b0.c:54:        case TMR32B0_CHAN_1: LPC_TMR32B0->PWMC |= TMR_PWM_ENA_MR1; break;
 +
./io_tmr32b0.c:55:        case TMR32B0_CHAN_2: LPC_TMR32B0->PWMC |= TMR_PWM_ENA_MR2; break;
 +
./io_tmr32b0.c:60:    // Configure PWM output on channels 0, 1, or 2.
 +
./io_tmr32b0.c:63:void IO_TMR32B0_ResetPWM(void)
 +
./io_tmr32b0.c:65:    LPC_TMR32B0->PWMC = 0;
 +
./io_tmr32b0.c:69:void IO_TMR32B0_StartPWM(uint32_t resolution)
 +
./io_tmr32b0.c:83:// Enable/disable interrupts for PWM:
 +
./io_tmr32b0.h:29:void IO_TMR32B0_EnablePWM(tmr32b0_chan_t chan);
 +
./io_tmr32b0.h:30:void IO_TMR32B0_ResetPWM(void);
 +
./io_tmr32b0.h:31:void IO_TMR32B0_StartPWM(uint32_t resolution);
 +
./io_tmr32b1.c:45:    // Configure PWM output on channels 0, 1, or 2.
 +
./io_tmr32b1.c:48:void IO_TMR32B1_EnablePWM(tmr32b1_chan_t chan)
 +
./io_tmr32b1.c:52:        case TMR32B1_CHAN_0: LPC_TMR32B1->PWMC |= TMR_PWM_ENA_MR0; break;
 +
./io_tmr32b1.c:53:        case TMR32B1_CHAN_1: LPC_TMR32B1->PWMC |= TMR_PWM_ENA_MR1; break;
 +
./io_tmr32b1.c:54:        case TMR32B1_CHAN_2: LPC_TMR32B1->PWMC |= TMR_PWM_ENA_MR2; break;
 +
./io_tmr32b1.c:59:    // Configure PWM output on channels 0, 1, or 2.
 +
./io_tmr32b1.c:62:void IO_TMR32B1_ResetPWM(void)
 +
./io_tmr32b1.c:64:    LPC_TMR32B1->PWMC = 0;
 +
./io_tmr32b1.c:68:void IO_TMR32B1_StartPWM(uint32_t resolution)
 +
./io_tmr32b1.c:82:// Enable/disable interrupts for PWM:
 +
./io_tmr32b1.h:29:void IO_TMR32B1_EnablePWM(tmr32b1_chan_t chan);
 +
./io_tmr32b1.h:30:void IO_TMR32B1_ResetPWM(void);
 +
./io_tmr32b1.h:31:void IO_TMR32B1_StartPWM(uint32_t resolution);
 +
</pre>
 +
 +
 +
Finding 1:
 +
 +
    1493 static con_ret_t Cmd_SetPWMLevel(char *pLine)
  
 +
Finding 2:
 +
 +
<pre>./apptask.c:1100:    if(OUTPUT_IS_MILLIAMP)
 +
./con_eeprom.h:23:#define OUTPUT_IS_VOLT        ((EEP_GetSelectedSwitchImage() & DIP_MA) == 0)
 +
./con_eeprom.h:24:#define OUTPUT_IS_MILLIAMP    ((EEP_GetSelectedSwitchImage() & DIP_MA) != 0)
 +
./con_tester.c:196:        (void *)ANALOG_OUTPUT_VOLT_CHANNEL, 0, DacWrite, NullRead},
 +
./con_tester.c:198:        (void *)ANALOG_OUTPUT_MA_CHANNEL, 0, DacWrite, NullRead},
 +
./console.c:634: IO_TMR32B1_Reset(ANALOG_OUTPUT_PRESCALER);
 +
./console.c:636: IO_TMR32B1_EnablePWM(ANALOG_OUTPUT_MA_CHANNEL);
 +
./console.c:637: IO_TMR32B1_EnablePWM(ANALOG_OUTPUT_VOLT_CHANNEL);
 +
./console.c:638: IO_TMR32B1_StartPWM(ANALOG_OUTPUT_RESOLUTION);
 +
./console.c:642: IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_MA_CHANNEL, STARTUP_PWM_VALUE);
 +
./console.c:643: IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_VOLT_CHANNEL, STARTUP_PWM_VALUE);
 +
./console.c:646: IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_MA_CHANNEL, 0.9F);
 +
./console.c:647: IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_VOLT_CHANNEL, STARTUP_PWM_VALUE);
 +
./console.c:774: IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_MA_CHANNEL, 0.50F);
 +
./console.c:775: IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_VOLT_CHANNEL, 0.50F);
 +
./drivers.c:467:    IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_MA_CHANNEL, level);
 +
./drivers.c:478:    IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_VOLT_CHANNEL, level);
 +
./drivers.h:324:#  define ANALOG_OUTPUT_CFG        CFG_DAC_TMR32B1  // uC PWM/DAC output
 +
</pre>
 +
 +
 +
Finding 3:
 +
 +
<pre>
 +
  1100    if(OUTPUT_IS_MILLIAMP)^M
 +
  1101    {^M
 +
  1102        // Here, calculate mA:^M
 +
  1103        outputUnits = percentFsr * 16.0F;    // 16.0 mA full scale^M
 +
  1104        pwmDutyCycle = (^M
 +
  1105            EEP_GetMaCalSlope() * outputUnits) + EEP_GetMaCalOffset();^M
 +
  1106        Signal_APP_SetOutputCurrentDac(pwmDutyCycle);^M
 +
  1107    }^M
 +
  1108    else^M
 +
  1109    {^M
 +
  1110        // Here, calculate volt.  Two ranges, 10V and 5V via DIP switch:^M
 +
  1111        if(VOLT_RANGE_10V)^M
 +
  1112        {^M
 +
  1113                        outputUnits = percentFsr * 10.0F;    // 10.0 volts full scale^M
 +
  1114        }^M
 +
  1115        else^M
 +
  1116        {^M
 +
  1117                        outputUnits = percentFsr * 5.0F;    // 5.0 volts full scale^M
 +
  1118        }^M
 +
  1119 ^M
 +
  1120        pwmDutyCycle = (^M
 +
  1121            EEP_GetVoltCalSlope() * outputUnits) + EEP_GetVoltCalOffset();^M
 +
  1122        Signal_APP_SetOutputVoltageDac(pwmDutyCycle);^M
 +
  1123    }^M
 +
</pre>
 +
 +
Finding 4:
 +
 +
<pre>
 +
veris@alta-spare-6:~/alta/pressure/px3/tags/Firmware/V1_1$ grep -n Signal_APP_SetOutputCurrentDac ./*
 +
grep: ./IAR_Debug: Is a directory
 +
grep: ./IAR_Release: Is a directory
 +
grep: ./Release: Is a directory
 +
./apptask.c:467:        Signal_APP_SetOutputCurrentDac(0.0F);
 +
./apptask.c:529: Signal_APP_SetOutputCurrentDac(0.0F);
 +
./apptask.c:983:            Signal_APP_SetOutputCurrentDac(0.0F);
 +
./apptask.c:1106:        Signal_APP_SetOutputCurrentDac(pwmDutyCycle);
 +
./apptask.h:98:void Signal_APP_SetOutputCurrentDac(float outputLevel);
 +
./drivers.c:461:void Signal_APP_SetOutputCurrentDac(float level)
 +
</pre>
 +
 +
Finding 5:
 +
 +
<pre>
 +
    461 void Signal_APP_SetOutputCurrentDac(float level)^M
 +
    462 {^M
 +
    463 #      if(CFG_PWM_REF_ENABLE != 0)^M
 +
    464        PollPwmReference();^M
 +
    465        level = CalibratePwmToReference(level);^M
 +
    466 #      endif^M
 +
    467    IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_MA_CHANNEL, level);^M
 +
    468    // Reflect it in tester registers.^M
 +
    469    CON_SetOutputCurrentDutyCycle(level);^M
 +
    470 }^M
 +
</pre>
 +
 +
veris@alta-spare-6:~/alta/pressure/px3/tags/Firmware/V1_1$ grep -n IO_TMR32B1_SetPwmLevel ./*
 +
grep: ./IAR_Debug: Is a directory
 +
grep: ./IAR_Release: Is a directory
 +
grep: ./Release: Is a directory
 +
./console.c:642: IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_MA_CHANNEL, STARTUP_PWM_VALUE);
 +
./console.c:643: IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_VOLT_CHANNEL, STARTUP_PWM_VALUE);
 +
./console.c:646: IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_MA_CHANNEL, 0.9F);
 +
./console.c:647: IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_VOLT_CHANNEL, STARTUP_PWM_VALUE);
 +
./console.c:774: IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_MA_CHANNEL, 0.50F);
 +
./console.c:775: IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_VOLT_CHANNEL, 0.50F);
 +
./drivers.c:358:    IO_TMR32B1_SetPwmLevel((tmr32b1_chan_t)chan, level);
 +
./drivers.c:467:    IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_MA_CHANNEL, level);
 +
./drivers.c:478:    IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_VOLT_CHANNEL, level);
 +
grep: ./initial-firmware-works: Is a directory
 +
./io_tmr32b1.c:252:void IO_TMR32B1_SetPwmLevel(tmr32b1_chan_t chan, float duty)
 +
./io_tmr32b1.h:48:void IO_TMR32B1_SetPwmLevel(tmr32b1_chan_t chan, float duty);
 +
 +
 +
History:
 +
 +
1005  grep -n IO_TriStateSet ./*.*
 +
1006  grep -n P0_7_DEFAULT ./*
 +
1007  grep -n P0_7_DIR ./*
 +
1008  grep -n DIR_INPUT ./*
 +
1009  grep -n DIR_OUTPUT ./* | grep define
 +
1010  locate UM10
 +
1011  locate LPC1114-UM
 +
1012  ls
 +
1013  grep -n ADC ./*
 +
1014  grep -n PWMC ./*
 +
1015  grep -n PWM ./*
 +
1016  kkkkkkkkk
 +
1017  grep -n OUTPUT ./*
 +
1018  grep -n Signal_APP_SetOutputCurrentDac ./*
 +
1019  grep -n IO_TMR32B1_SetPwmLevel ./*
 +
1020  history
 +
 +
 +
Finding 6:
 +
 +
<pre>
 +
    252 void IO_TMR32B1_SetPwmLevel(tmr32b1_chan_t chan, float duty)^M
 +
    253 {^M
 +
    254    uint32_t counts;^M
 +
    255 ^M
 +
    256    // Convert float duty cycle to integer counts for the counter/^M
 +
    257    // timer.^M
 +
    258    counts = (uint32_t)(duty * mResolution);^M
 +
    259 ^M
 +
    260    // Counter counts the other way, so invert.^M
 +
    261    counts = mResolution - counts;^M
 +
    262 ^M
 +
    263 //    CON_TxChar(' ');^M
 +
    264 //    CON_TxHexWord((uint16_t)counts);^M
 +
    265 ^M
 +
    266    switch(chan)^M
 +
    267    {^M
 +
    268        case TMR32B1_CHAN_0:^M
 +
    269            LPC_TMR32B1->MR0 = counts;^M
 +
    270            break;^M
 +
    271 ^M
 +
    272        case TMR32B1_CHAN_1:^M
 +
    273            LPC_TMR32B1->MR1 = counts;^M
 +
    274            break;^M
 +
    275 ^M
 +
    276        case TMR32B1_CHAN_2:^M
 +
    277            LPC_TMR32B1->MR2 = counts;^M
 +
    278            break;^M
 +
    279 ^M
 +
    280        default: FATAL(0); break;^M
 +
    281    }^M
 +
    282 }^M
 +
</pre>
 +
 +
 +
<pre>
 +
 +
In file <code>io_conf_lqfp48.c</code>:
 +
 +
  LPC_IOCON->PIO1_1 = P1_1_CONFIG | A2D_RESERVED;
 +
 +
 +
In file <code>io_def_0C.h</code>:
 +
 +
  #define P1_1_CONFIG    IO_CONFIG(P1_1, FUNC_CT32B1_MAT0, MODE_FLOAT, HYST_DIS)
 +
 +
 +
In file <code>io_conf_lqfp48.h</code>:
 +
 +
  #define IO_CONFIG(PORT, FUNC, MODE, HYST) (FUNC ## _ ## PORT | MODE | HYST)
 +
 +
</pre>
 +
 +
 +
 +
2018-10-31
 +
 +
How do these signal routines from source file drivers.c affect firmware operation?  They all appear to be empty routines, without any statements to execute:
 +
 +
<pre>
 +
    265 //*********************************************************************^M
 +
    266 //      Timer Signals^M
 +
    267 //* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *^M
 +
    268 ^M
 +
    269 #if(CFG_ENABLE_TIMER_16B0 != 0)^M
 +
    270 void Signal_TMR16B0_MAT0_Interrupt(void){}^M
 +
    271 void Signal_TMR16B0_MAT1_Interrupt(void){}^M
 +
    272 void Signal_TMR16B0_MAT2_Interrupt(void){}^M
 +
    273 void Signal_TMR16B0_MAT3_Interrupt(void){}^M
 +
    274 #endif^M
 +
    275 ^M
 +
    276 #if(CFG_ENABLE_TIMER_16B1 != 0)^M
 +
    277 void Signal_TMR16B1_MAT0_Interrupt(void){}^M
 +
    278 void Signal_TMR16B1_MAT1_Interrupt(void){}^M
 +
    279 void Signal_TMR16B1_MAT2_Interrupt(void){}^M
 +
    280 void Signal_TMR16B1_MAT3_Interrupt(void){}^M
 +
    281 #endif^M
 +
    282 ^M
 +
    283 #if(CFG_ENABLE_TIMER_32B0 != 0)^M
 +
    284 void Signal_TMR32B0_MAT0_Interrupt(void){}^M
 +
    285 void Signal_TMR32B0_MAT1_Interrupt(void){}^M
 +
    286 void Signal_TMR32B0_MAT2_Interrupt(void){}^M
 +
    287 void Signal_TMR32B0_MAT3_Interrupt(void){}^M
 +
    288 #endif^M
 +
    289 ^M
 +
    290 #if(CFG_ENABLE_TIMER_32B1 != 0)^M
 +
    291 void Signal_TMR32B1_MAT0_Interrupt(void){}^M
 +
    292 void Signal_TMR32B1_MAT1_Interrupt(void){}^M
 +
    293 void Signal_TMR32B1_MAT2_Interrupt(void){}^M
 +
    294 void Signal_TMR32B1_MAT3_Interrupt(void){}^M
 +
    295 #endif^M
 +
</pre>
 +
 +
 +
 +
-->
  
−
So where is <code>pGPIO</code> defined?
 
  
  
 
<!-- comment -->
 
<!-- comment -->

Latest revision as of 20:57, 31 October 2018

CMSIS Library Routines and Details,
LPC1xxx Board Routines
notes started 2018-10-25 THU


LPC11U14 board routines . . .


First search, looking for how NXP demo toggles a given GPIO: 

user:~/Downloads/nxp/lpcopen$ grep -nr Board_LED_Toggle ./*

./nxp_lpcxpresso_11u14_board_lib/src/board.c:137:void Board_LED_Toggle(uint8_t LEDNumber)
./nxp_lpcxpresso_11u14_board_lib/inc/board_api.h:112:void Board_LED_Toggle(uint8_t LEDNumber);
./nxp_lpcxpresso_11u14_periph_clkout/example/src/clkout.c:77:		Board_LED_Toggle(0);
./nxp_lpcxpresso_11u14_periph_pinint/example/src/pinint.c:187:		Board_LED_Toggle(0);
./nxp_lpcxpresso_11u14_periph_uart/example/src/uart.c:135:				Board_LED_Toggle(0);/* Toggle LED if the TX FIFO is full */
./nxp_lpcxpresso_11u14_periph_watchdog/example/src/watchdog.c:65:		Board_LED_Toggle(0);
./nxp_lpcxpresso_11u14_periph_watchdog/example/src/watchdog.c:72:	Board_LED_Toggle(0);

The routine itself in file ~/Downloads/nxp/lpcopen/nxp_lpcxpresso_11u14_board_lib/src/board.c: 

    137 void Board_LED_Toggle(uint8_t LEDNumber)
    138 {^M
    139         if (LEDNumber == 0)^M
    140                 Chip_GPIO_SetPinToggle(LPC_GPIO, 0, 7);
    141 }

Next search: 

$ grep -nr Chip_GPIO_SetPinToggle ./*

user:~/Downloads/nxp/lpcopen$ grep -nr Chip_GPIO_SetPinToggle ./*
./lpc_chip_11uxx_lib/inc/gpio_11xx_1.h:447:STATIC INLINE void Chip_GPIO_SetPinToggle(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
Binary file ./nxp_lpcxpresso_11u14_board_lib/src/.board.c.swp matches
./nxp_lpcxpresso_11u14_board_lib/src/board.c:140:		Chip_GPIO_SetPinToggle(LPC_GPIO, 0, 7);

And the lower level routine itself in file ./lpc_chip_11uxx_lib/inc/gpio_11xx_1.h: 

    438 /**^M
    439  * @brief       Toggle an individual GPIO output pin to the opposite state^M
    440  * @param       pGPIO   : The base of GPIO peripheral on the chip^M
    441  * @param       port    : GPIO Port number where @a pin is located^M
    442  * @param       pin             : pin number (0..n) to toggle^M
    443  * @return      None^M
    444  * @note        Any bit set as a '0' will not have it's state changed. This only^M
    445  * applies to ports configured as an output.^M
    446  */^M
    447 STATIC INLINE void Chip_GPIO_SetPinToggle(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)^M
    448 {^M
    449         pGPIO->NOT[port] = (1 << pin);^M
    450 }^M

So where is pGPIO defined?


^ LPC_GPIO_TYPEDEF

$ pwd

.../Firmware/V1_1$

$ grep -nr LPC_GPIO_TypeDef ./* | grep LPC11

./LPC11xx.h:295:} LPC_GPIO_TypeDef;
./LPC11xx.h:490:#define LPC_GPIO0             ((LPC_GPIO_TypeDef   *) LPC_GPIO0_BASE )
./LPC11xx.h:491:#define LPC_GPIO1             ((LPC_GPIO_TypeDef   *) LPC_GPIO1_BASE )
./LPC11xx.h:492:#define LPC_GPIO2             ((LPC_GPIO_TypeDef   *) LPC_GPIO2_BASE )
./LPC11xx.h:493:#define LPC_GPIO3             ((LPC_GPIO_TypeDef   *) LPC_GPIO3_BASE )
Binary file ./Release/Obj/sysconfig_LPC11xx.pbi matches
./initial-firmware-works/Unit_Test/apptask/LPC11xx.h:192:} LPC_GPIO_TypeDef;
./initial-firmware-works/Unit_Test/apptask/LPC11xx.h:204:extern LPC_GPIO_TypeDef gpio;
./initial-firmware-works/Unit_Test/px3_system/LPC11xx.h:192:} LPC_GPIO_TypeDef;
./initial-firmware-works/Unit_Test/px3_system/LPC11xx.h:204:extern LPC_GPIO_TypeDef gpio;
./initial-firmware-works/FloatingPoint/LPC11xx.h:295:} LPC_GPIO_TypeDef;
./initial-firmware-works/FloatingPoint/LPC11xx.h:490:#define LPC_GPIO0             ((LPC_GPIO_TypeDef   *) LPC_GPIO0_BASE )
./initial-firmware-works/FloatingPoint/LPC11xx.h:491:#define LPC_GPIO1             ((LPC_GPIO_TypeDef   *) LPC_GPIO1_BASE )
./initial-firmware-works/FloatingPoint/LPC11xx.h:492:#define LPC_GPIO2             ((LPC_GPIO_TypeDef   *) LPC_GPIO2_BASE )
./initial-firmware-works/FloatingPoint/LPC11xx.h:493:#define LPC_GPIO3             ((LPC_GPIO_TypeDef   *) LPC_GPIO3_BASE )
./initial-firmware-works/Obsolete (FixedPoint)/LPC11xx.h:295:} LPC_GPIO_TypeDef;
./initial-firmware-works/Obsolete (FixedPoint)/LPC11xx.h:490:#define LPC_GPIO0             ((LPC_GPIO_TypeDef   *) LPC_GPIO0_BASE )
./initial-firmware-works/Obsolete (FixedPoint)/LPC11xx.h:491:#define LPC_GPIO1             ((LPC_GPIO_TypeDef   *) LPC_GPIO1_BASE )
./initial-firmware-works/Obsolete (FixedPoint)/LPC11xx.h:492:#define LPC_GPIO2             ((LPC_GPIO_TypeDef   *) LPC_GPIO2_BASE )
./initial-firmware-works/Obsolete (FixedPoint)/LPC11xx.h:493:#define LPC_GPIO3             ((LPC_GPIO_TypeDef   *) LPC_GPIO3_BASE )


Using Timers As Pulsewidth Modulators

Findings to go here later . . .



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