Difference between revisions of "Bootloading"

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               GND  . . . CN5 pin 7 and others
 
               GND  . . . CN5 pin 7 and others
  
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2022-08-30 TUE -
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Looking for how to enable USART1 on STM32WL55JC.  Strange, we see in [our+app]/build/zephyr/zephyr.dts a reference to:
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<pre>
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179                        lpuart1_tx_pa2: lpuart1_tx_pa2 {
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180                                pinmux = < 0x48 >;
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181                                bias-pull-up;
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182                                phandle = < 0x4 >;
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183                        };
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</pre>
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. . . which is one of the pins called out in the board level device tree file [zephyr_3p1p0_root]/boards/arm/nucleo_wl55jc.dts, for lpuart1 device node.  We want to enable &amp;usart1, and it looks like we'll want to specify RX and TX pins similarly.  But where and how is 'lpuart1_tx_pa2' defined?
  
 
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Revision as of 04:49, 31 August 2022

2022-08-01 Notes on bootloaders for microcontrollers

Keywords: bootloader :: bootloaders :: serial bootloader :: serial bootloading


A starting point, which links to five articles on differing bootloading approaches:


2022-08-03

What is a serial bootloader and how is it used?

Following link gives Silabs example, but is not a good general explanation:


^ Atmel bootloader


^ STMicro bootloaders

Following is an interesting link in that it appears to cause web browser to download the linked pdf file, and then subsequent visits to this link redirect to the local downloaded copy:


QUESTION: How to enter bootloader? activate bootloader for STM32 parts?

ANSWER: In a general sense STM32 bootloader activation depends often on both certain config register bits settings and also one or two pin states at power up. For the STM32WL55, document AN2606 pages 28 and 370 give us a starting point for the names of the configuration registers in which to set or clear certain bits, and the name of the pin, BOOT0, to hold high or low at power up. Each MCU family or line has variations on this theme . . .


With the STM32WL55xx Nucleo board, STMicro's AN2606 application notes document says that USART1 is enabled with RX and TX lines assigned to PA10 and PA9 respectively. These MCU pins map to connectors and connector pins:

USART1 TX --> PA9  . . . CN5 pin 2
USART1 RX --> PA10 . . . CN8 pin 3
              GND  . . . CN5 pin 7 and others

2022-08-30 TUE - Looking for how to enable USART1 on STM32WL55JC. Strange, we see in [our+app]/build/zephyr/zephyr.dts a reference to:

179                         lpuart1_tx_pa2: lpuart1_tx_pa2 {
180                                 pinmux = < 0x48 >;
181                                 bias-pull-up;
182                                 phandle = < 0x4 >;
183                         };

. . . which is one of the pins called out in the board level device tree file [zephyr_3p1p0_root]/boards/arm/nucleo_wl55jc.dts, for lpuart1 device node. We want to enable &usart1, and it looks like we'll want to specify RX and TX pins similarly. But where and how is 'lpuart1_tx_pa2' defined?


^ RP2040 bootloaders


^ References