ARM processor

^ OVERVIEW

This page for notes on ARM processor architecture, and related ARM IP works.

ARM Architecture and Instruction Set Notes

• http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0040d/Cabdcdci.html . . . ARM BX "branch and exchange" instruction (branch and change to thumb mode)

[ ] . . . search for Armv8-M Architecture Reference Manual ID28092022

^ Advanced Hardware Bus AHB

ARM architecture and related IP, link to AHB paper by Rinku 1, Pawan Kumar Dahiya 2

• https://www.iosrjournals.org/iosr-jvlsi/papers/vol7-issue4/Version-1/H0704015156.pdf

^ Synchronization Primitives LDREX and STREX

ARM Synchronization Primitives LDREX and STREX, split a normally atomic memory write operation and allow for checking whether other Processing Elements or "bus primaries" (note 1) are also accessing the given memory location. From the short documentations linked below, it looks like LDREX updates local and global resource access monitors in certain ARM variants, and STREX either succeeds or fails based on checking one or both of those monitors, depending on whether the memory or resource is shared or not shared among multiple processing elements (PEs).

Article locally numbered (3) in the following list of URLs introduces a comparative concept in its text "The Data Memory Barrier existed before ARMv7 as a cp15 operation, but ARMv7 introduced a dedicated instruction, DMB."

• (1) https://developer.arm.com/documentation/dht0008/a/ch01s02s01
• (2) https://developer.arm.com/documentation/dht0008/a/arm-synchronization-primitives/exclusive-accesses/exclusive-monitors
• (3) https://developer.arm.com/documentation/dht0008/a/arm-synchronization-primitives/exclusive-accesses/memory-barriers