Iis2dh
Notes on . . .
Excerpt on accelerator configurations from this developer: mhackney (Community Member) Edited by ST Community July 21, 2018 at 5:26 PM Posted on January 02, 2017 at 16:21
Ok, I overlooked the data sheet that Low Power mode is 8-bit data output. But that still does not explain why the data is not left aligned?
Also, here is my complete configuration to sanity check:
// setup CTRL_REG1
accelerometer_write(CTRL_REG1, 0b10011100); // ODR 5.376kHz in LPMode [7-4] Low power enable [3] Z enable [2]
// setup CTRL_REG2
accelerometer_write(CTRL_REG2, 0b00110001); //
// setup CTRL_REG3
accelerometer_write(CTRL_REG3, 0b01000000); // AOI (And Or Interrupt) on INT1 en [6]
// setup CTRL_REG6
accelerometer_write(CTRL_REG6, 0b00000000); //
// setup CTRL_REG4
accelerometer_write(CTRL_REG4, 0b00110000); // Full-scale selection 16G [5-4]
// setup CTRL_REG5
accelerometer_write(CTRL_REG5, 0b01001010); // FIFO enable [6] Latch INT1 [3]
// setup INT1_CFG
accelerometer_write(INT1_CFG, 0b00100000); // ZHIE enabled [5]
// setup INT1_THS
accelerometer_write(INT1_THS, Z_PROBE_SENSITIVITY); // 40
// setup INT1_DURATION
accelerometer_write(INT1_DURATION, 0);
