Difference between revisions of "Nxp chip library routines"

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m (→‎Using Timers As Pulsewidth Modulators)
m (→‎Using Timers As Pulsewidth Modulators)
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</pre>
 
</pre>
  
 +
Finding 5:
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 +
<pre>
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    461 void Signal_APP_SetOutputCurrentDac(float level)^M
 +
    462 {^M
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    463 #      if(CFG_PWM_REF_ENABLE != 0)^M
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    464        PollPwmReference();^M
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    465        level = CalibratePwmToReference(level);^M
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    466 #      endif^M
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    467    IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_MA_CHANNEL, level);^M
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    468    // Reflect it in tester registers.^M
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    469    CON_SetOutputCurrentDutyCycle(level);^M
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    470 }^M
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</pre>
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 +
veris@alta-spare-6:~/alta/pressure/px3/tags/Firmware/V1_1$ grep -n IO_TMR32B1_SetPwmLevel ./*
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grep: ./IAR_Debug: Is a directory
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grep: ./IAR_Release: Is a directory
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grep: ./Release: Is a directory
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./console.c:642: IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_MA_CHANNEL, STARTUP_PWM_VALUE);
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./console.c:643: IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_VOLT_CHANNEL, STARTUP_PWM_VALUE);
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./console.c:646: IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_MA_CHANNEL, 0.9F);
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./console.c:647: IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_VOLT_CHANNEL, STARTUP_PWM_VALUE);
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./console.c:774: IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_MA_CHANNEL, 0.50F);
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./console.c:775: IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_VOLT_CHANNEL, 0.50F);
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./drivers.c:358:    IO_TMR32B1_SetPwmLevel((tmr32b1_chan_t)chan, level);
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./drivers.c:467:    IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_MA_CHANNEL, level);
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./drivers.c:478:    IO_TMR32B1_SetPwmLevel(ANALOG_OUTPUT_VOLT_CHANNEL, level);
 +
grep: ./initial-firmware-works: Is a directory
 +
./io_tmr32b1.c:252:void IO_TMR32B1_SetPwmLevel(tmr32b1_chan_t chan, float duty)
 +
./io_tmr32b1.h:48:void IO_TMR32B1_SetPwmLevel(tmr32b1_chan_t chan, float duty);
 +
 +
 +
History:
 +
 +
1005  grep -n IO_TriStateSet ./*.*
 +
1006  grep -n P0_7_DEFAULT ./*
 +
1007  grep -n P0_7_DIR ./*
 +
1008  grep -n DIR_INPUT ./*
 +
1009  grep -n DIR_OUTPUT ./* | grep define
 +
1010  locate UM10
 +
1011  locate LPC1114-UM
 +
1012  ls
 +
1013  grep -n ADC ./*
 +
1014  grep -n PWMC ./*
 +
1015  grep -n PWM ./*
 +
1016  kkkkkkkkk
 +
1017  grep -n OUTPUT ./*
 +
1018  grep -n Signal_APP_SetOutputCurrentDac ./*
 +
1019  grep -n IO_TMR32B1_SetPwmLevel ./*
 +
1020  history
  
  

Revision as of 23:08, 26 October 2018

CMSIS Library Routines and Details,
LPC1xxx Board Routines
notes started 2018-10-25 THU


LPC11U14 board routines . . .


First search, looking for how NXP demo toggles a given GPIO: 

user:~/Downloads/nxp/lpcopen$ grep -nr Board_LED_Toggle ./*

./nxp_lpcxpresso_11u14_board_lib/src/board.c:137:void Board_LED_Toggle(uint8_t LEDNumber)
./nxp_lpcxpresso_11u14_board_lib/inc/board_api.h:112:void Board_LED_Toggle(uint8_t LEDNumber);
./nxp_lpcxpresso_11u14_periph_clkout/example/src/clkout.c:77:		Board_LED_Toggle(0);
./nxp_lpcxpresso_11u14_periph_pinint/example/src/pinint.c:187:		Board_LED_Toggle(0);
./nxp_lpcxpresso_11u14_periph_uart/example/src/uart.c:135:				Board_LED_Toggle(0);/* Toggle LED if the TX FIFO is full */
./nxp_lpcxpresso_11u14_periph_watchdog/example/src/watchdog.c:65:		Board_LED_Toggle(0);
./nxp_lpcxpresso_11u14_periph_watchdog/example/src/watchdog.c:72:	Board_LED_Toggle(0);

The routine itself in file ~/Downloads/nxp/lpcopen/nxp_lpcxpresso_11u14_board_lib/src/board.c: 

    137 void Board_LED_Toggle(uint8_t LEDNumber)
    138 {^M
    139         if (LEDNumber == 0)^M
    140                 Chip_GPIO_SetPinToggle(LPC_GPIO, 0, 7);
    141 }

Next search: 

$ grep -nr Chip_GPIO_SetPinToggle ./*

user:~/Downloads/nxp/lpcopen$ grep -nr Chip_GPIO_SetPinToggle ./*
./lpc_chip_11uxx_lib/inc/gpio_11xx_1.h:447:STATIC INLINE void Chip_GPIO_SetPinToggle(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
Binary file ./nxp_lpcxpresso_11u14_board_lib/src/.board.c.swp matches
./nxp_lpcxpresso_11u14_board_lib/src/board.c:140:		Chip_GPIO_SetPinToggle(LPC_GPIO, 0, 7);

And the lower level routine itself in file ./lpc_chip_11uxx_lib/inc/gpio_11xx_1.h: 

    438 /**^M
    439  * @brief       Toggle an individual GPIO output pin to the opposite state^M
    440  * @param       pGPIO   : The base of GPIO peripheral on the chip^M
    441  * @param       port    : GPIO Port number where @a pin is located^M
    442  * @param       pin             : pin number (0..n) to toggle^M
    443  * @return      None^M
    444  * @note        Any bit set as a '0' will not have it's state changed. This only^M
    445  * applies to ports configured as an output.^M
    446  */^M
    447 STATIC INLINE void Chip_GPIO_SetPinToggle(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)^M
    448 {^M
    449         pGPIO->NOT[port] = (1 << pin);^M
    450 }^M

So where is pGPIO defined?


^ LPC_GPIO_TYPEDEF

$ pwd

.../Firmware/V1_1$

$ grep -nr LPC_GPIO_TypeDef ./* | grep LPC11

./LPC11xx.h:295:} LPC_GPIO_TypeDef;
./LPC11xx.h:490:#define LPC_GPIO0             ((LPC_GPIO_TypeDef   *) LPC_GPIO0_BASE )
./LPC11xx.h:491:#define LPC_GPIO1             ((LPC_GPIO_TypeDef   *) LPC_GPIO1_BASE )
./LPC11xx.h:492:#define LPC_GPIO2             ((LPC_GPIO_TypeDef   *) LPC_GPIO2_BASE )
./LPC11xx.h:493:#define LPC_GPIO3             ((LPC_GPIO_TypeDef   *) LPC_GPIO3_BASE )
Binary file ./Release/Obj/sysconfig_LPC11xx.pbi matches
./initial-firmware-works/Unit_Test/apptask/LPC11xx.h:192:} LPC_GPIO_TypeDef;
./initial-firmware-works/Unit_Test/apptask/LPC11xx.h:204:extern LPC_GPIO_TypeDef gpio;
./initial-firmware-works/Unit_Test/px3_system/LPC11xx.h:192:} LPC_GPIO_TypeDef;
./initial-firmware-works/Unit_Test/px3_system/LPC11xx.h:204:extern LPC_GPIO_TypeDef gpio;
./initial-firmware-works/FloatingPoint/LPC11xx.h:295:} LPC_GPIO_TypeDef;
./initial-firmware-works/FloatingPoint/LPC11xx.h:490:#define LPC_GPIO0             ((LPC_GPIO_TypeDef   *) LPC_GPIO0_BASE )
./initial-firmware-works/FloatingPoint/LPC11xx.h:491:#define LPC_GPIO1             ((LPC_GPIO_TypeDef   *) LPC_GPIO1_BASE )
./initial-firmware-works/FloatingPoint/LPC11xx.h:492:#define LPC_GPIO2             ((LPC_GPIO_TypeDef   *) LPC_GPIO2_BASE )
./initial-firmware-works/FloatingPoint/LPC11xx.h:493:#define LPC_GPIO3             ((LPC_GPIO_TypeDef   *) LPC_GPIO3_BASE )
./initial-firmware-works/Obsolete (FixedPoint)/LPC11xx.h:295:} LPC_GPIO_TypeDef;
./initial-firmware-works/Obsolete (FixedPoint)/LPC11xx.h:490:#define LPC_GPIO0             ((LPC_GPIO_TypeDef   *) LPC_GPIO0_BASE )
./initial-firmware-works/Obsolete (FixedPoint)/LPC11xx.h:491:#define LPC_GPIO1             ((LPC_GPIO_TypeDef   *) LPC_GPIO1_BASE )
./initial-firmware-works/Obsolete (FixedPoint)/LPC11xx.h:492:#define LPC_GPIO2             ((LPC_GPIO_TypeDef   *) LPC_GPIO2_BASE )
./initial-firmware-works/Obsolete (FixedPoint)/LPC11xx.h:493:#define LPC_GPIO3             ((LPC_GPIO_TypeDef   *) LPC_GPIO3_BASE )


Using Timers As Pulsewidth Modulators

Findings to go here later . . .



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