Difference between revisions of "Device tree from scratch"
m (→Reference: Add link to nRF9160 memory map.) |
m (→^ Nordic Semi nRF9160) |
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| Line 12: | Line 12: | ||
Not sure for what DPPI stands, but this device in nRF9160 SoC device tree file `` has a simple node entry. Code excerpt from https://github.com/zephyrproject-rtos/zephyr/blob/main/dts/arm/nordic/nrf9160_common.dtsi#L31: | Not sure for what DPPI stands, but this device in nRF9160 SoC device tree file `` has a simple node entry. Code excerpt from https://github.com/zephyrproject-rtos/zephyr/blob/main/dts/arm/nordic/nrf9160_common.dtsi#L31: | ||
| + | [https://github.com/zephyrproject-rtos/zephyr/blob/main/dts/arm/nordic/nrf9160_common.dtsi#L31 dts excerpt for nRF9160 dppi device] | ||
<pre> | <pre> | ||
dppic: dppic@17000 { | dppic: dppic@17000 { | ||
| Line 23: | Line 24: | ||
| + | Device tree source excerpt for nRF9160 SPI peripheral. Looking over this much of the detail like all the specific configuration registers is left out of device tree. These hardware features need to be implemented in the given device' driver code: | ||
| + | |||
| + | <i> [https://github.com/zephyrproject-rtos/zephyr/blob/main/dts/arm/nordic/nrf9160_common.dtsi#L209 dts excerpt] </i> | ||
| + | <pre> | ||
| + | spi0: spi@8000 { | ||
| + | /* | ||
| + | * This spi node can be either SPIM or SPIS, for the user to pick: | ||
| + | * compatible = "nordic,nrf-spim" or | ||
| + | * "nordic,nrf-spis". | ||
| + | */ | ||
| + | compatible = "nordic,nrf-spim"; | ||
| + | #address-cells = <1>; | ||
| + | #size-cells = <0>; | ||
| + | reg = <0x8000 0x1000>; | ||
| + | interrupts = <8 NRF_DEFAULT_IRQ_PRIORITY>; | ||
| + | max-frequency = <DT_FREQ_M(8)>; | ||
| + | status = "disabled"; | ||
| + | }; | ||
| + | </pre> | ||
Revision as of 22:28, 15 August 2022
2022-08-15 Monday
How to Create Device Tree Files for New MCUs
^ Overview
Starting local article on how to craft a correct and complete device tree file set for an MCU not yet supported by Zephyr RTOS. First notes here will reference examples of device tree source files various supported MCUs, plus corresponding datasheet sections pertaining to given MCUs.
^ Nordic Semi nRF9160
Not sure for what DPPI stands, but this device in nRF9160 SoC device tree file `` has a simple node entry. Code excerpt from https://github.com/zephyrproject-rtos/zephyr/blob/main/dts/arm/nordic/nrf9160_common.dtsi#L31:
dts excerpt for nRF9160 dppi device
dppic: dppic@17000 {
compatible = "nordic,nrf-dppic";
reg = <0x17000 0x1000>;
status = "okay";
};
Looking at the `reg` property we find 0x17000 value called out. From personal memory we know this is the memory mapped address or offset from some base address. We'll look for this offset in Nordic's datasheet on the nRF9160 application core . . .
Device tree source excerpt for nRF9160 SPI peripheral. Looking over this much of the detail like all the specific configuration registers is left out of device tree. These hardware features need to be implemented in the given device' driver code:
spi0: spi@8000 {
/*
* This spi node can be either SPIM or SPIS, for the user to pick:
* compatible = "nordic,nrf-spim" or
* "nordic,nrf-spis".
*/
compatible = "nordic,nrf-spim";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x8000 0x1000>;
interrupts = <8 NRF_DEFAULT_IRQ_PRIORITY>;
max-frequency = <DT_FREQ_M(8)>;
status = "disabled";
};
Reference
- https://infocenter.nordicsemi.com/topic/ps_nrf9160/memory.html
- https://infocenter.nordicsemi.com/topic/ps_nrf9160/dppi.html Nordic Semi documentation on Distributed Programmable Peripheral Interconnect
- https://github.com/zephyrproject-rtos/hal_nordic/blob/master/nrfx/hal/nrf_dppi.h link to hal_nordic code repository
