Difference between revisions of "ARM processor"

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== OVERVIEW ==
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== [[#top|^]] OVERVIEW ==
  
 
This page for notes on ARM processor architecture, and related ARM IP works.
 
This page for notes on ARM processor architecture, and related ARM IP works.
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== Advanced Hardware Bus AHB ==
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== [[#top|^]] Advanced Hardware Bus AHB ==
  
 
ARM architecture and related IP, link to AHB paper by Rinku 1, Pawan Kumar Dahiya 2
 
ARM architecture and related IP, link to AHB paper by Rinku 1, Pawan Kumar Dahiya 2
  
 
*  https://www.iosrjournals.org/iosr-jvlsi/papers/vol7-issue4/Version-1/H0704015156.pdf
 
*  https://www.iosrjournals.org/iosr-jvlsi/papers/vol7-issue4/Version-1/H0704015156.pdf
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== [[#top|^]] Synchronization Primitives LDREX and STREX ==
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ARM Synchronization Primitives LDREX and STREX, split a normally atomic memory write operation and allow for checking whether other Processing Elements or "bus primaries" <i>(note 1)</i> are also accessing the given memory location.  From the short documentations linked below, it looks like LDREX updates local and global resource access monitors in certain ARM variants, and STREX either succeeds or fails based on checking one or both of those monitors, depending on whether the memory or resource is shared or not shared among multiple processing elements (PEs).
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Article locally numbered (3) in the following list of URLs introduces a comparative concept in its text "The Data Memory Barrier existed before ARMv7 as a cp15 operation, but ARMv7 introduced a dedicated instruction, DMB."
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<ul>
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*  (1) https://developer.arm.com/documentation/dht0008/a/ch01s02s01
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*  (2) https://developer.arm.com/documentation/dht0008/a/arm-synchronization-primitives/exclusive-accesses/exclusive-monitors
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*  (3) https://developer.arm.com/documentation/dht0008/a/arm-synchronization-primitives/exclusive-accesses/memory-barriers
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</ul>
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Abbreviations:
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{| class="wikitable"
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|-
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|abbr ERG || Exclusive Reservation Granuale, refers to smallest memory regions which Exclusive Monitors are able to tag for exclusive access || ARM Developer docs
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|-
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|abbr SCU || Snoop Control Unit || ARM Developer docs
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|-
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|abbr&nbsp;KPCR || Kernel Processor Control Region || arm_assembler_primer.html
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|}
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2023-04-17 Monday<br />
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Searching for an example assembly code snippet calling `STREX` and branching conditionally based on result.  Search string is "arm assembly strex and branch example".  First found results include:
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*  https://codemachine.com/articles/arm_assembler_primer.html
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*  https://developer.arm.com/documentation/dui0489/c/arm-and-thumb-instructions/memory-access-instructions/ldrex-and-strex
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Article by Raymond Chen:
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*  https://devblogs.microsoft.com/oldnewthing/20210614-00/?p=105307
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Excerpt:
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<pre>
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    MOV r1, #0x1                ; load the 'lock taken' value
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try
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    LDREX r0, [LockAddr]        ; load the lock value
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    CMP r0, #0                  ; is the lock free?
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    STREXEQ r0, r1, [LockAddr]  ; try and claim the lock
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    CMPEQ r0, #0                ; did this succeed?
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    BNE try                    ; no - try again
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    ....                        ; yes - we have the lock
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</pre>
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Latest revision as of 20:49, 17 April 2023

^ OVERVIEW

This page for notes on ARM processor architecture, and related ARM IP works.


ARM Architecture and Instruction Set Notes

[ ] . . . search for Armv8-M Architecture Reference Manual ID28092022


^ Advanced Hardware Bus AHB

ARM architecture and related IP, link to AHB paper by Rinku 1, Pawan Kumar Dahiya 2


^ Synchronization Primitives LDREX and STREX

ARM Synchronization Primitives LDREX and STREX, split a normally atomic memory write operation and allow for checking whether other Processing Elements or "bus primaries" (note 1) are also accessing the given memory location. From the short documentations linked below, it looks like LDREX updates local and global resource access monitors in certain ARM variants, and STREX either succeeds or fails based on checking one or both of those monitors, depending on whether the memory or resource is shared or not shared among multiple processing elements (PEs).

Article locally numbered (3) in the following list of URLs introduces a comparative concept in its text "The Data Memory Barrier existed before ARMv7 as a cp15 operation, but ARMv7 introduced a dedicated instruction, DMB."

Abbreviations:

abbr ERG Exclusive Reservation Granuale, refers to smallest memory regions which Exclusive Monitors are able to tag for exclusive access ARM Developer docs
abbr SCU Snoop Control Unit ARM Developer docs
abbr KPCR Kernel Processor Control Region arm_assembler_primer.html

2023-04-17 Monday

Searching for an example assembly code snippet calling `STREX` and branching conditionally based on result. Search string is "arm assembly strex and branch example". First found results include:

Article by Raymond Chen:

Excerpt: 

    MOV r1, #0x1                ; load the 'lock taken' value
try
    LDREX r0, [LockAddr]        ; load the lock value
    CMP r0, #0                  ; is the lock free?
    STREXEQ r0, r1, [LockAddr]  ; try and claim the lock
    CMPEQ r0, #0                ; did this succeed?
    BNE try                     ; no - try again
    ....                        ; yes - we have the lock




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